
// Library name: VLSI_Project
// Cell name: 2_to_1_Mux
// View name: schematic
subckt VLSI_Project_2_to_1_Mux_schematic Bulk out s sb x0 x1
    M1 (out s x1 Bulk) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M0 (out sb x0 Bulk) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
ends VLSI_Project_2_to_1_Mux_schematic
// End of subcircuit definition.

// Library name: VLSI_Project
// Cell name: 16_to_1_Mux
// View name: schematic
subckt VLSI_Project_16_to_1_Mux_schematic Bulk out s0 s1 s2 s3 sb0 sb1 sb2 \
        sb3 x0 x1 x10 x11 x12 x13 x14 x15 x2 x3 x4 x5 x6 x7 x8 x9
    I14 (Bulk out s3 sb3 net30 net35) VLSI_Project_2_to_1_Mux_schematic
    I13 (Bulk net35 s2 sb2 net53 net37) VLSI_Project_2_to_1_Mux_schematic
    I12 (Bulk net30 s2 sb2 net42 net59) VLSI_Project_2_to_1_Mux_schematic
    I11 (Bulk net37 s1 sb1 net48 net49) VLSI_Project_2_to_1_Mux_schematic
    I10 (Bulk net53 s1 sb1 net54 net83) VLSI_Project_2_to_1_Mux_schematic
    I9 (Bulk net59 s1 sb1 net101 net95) VLSI_Project_2_to_1_Mux_schematic
    I8 (Bulk net42 s1 sb1 net66 net67) VLSI_Project_2_to_1_Mux_schematic
    I7 (Bulk net49 s0 sb0 x14 x15) VLSI_Project_2_to_1_Mux_schematic
    I6 (Bulk net48 s0 sb0 x12 x13) VLSI_Project_2_to_1_Mux_schematic
    I5 (Bulk net83 s0 sb0 x10 x11) VLSI_Project_2_to_1_Mux_schematic
    I4 (Bulk net54 s0 sb0 x8 x9) VLSI_Project_2_to_1_Mux_schematic
    I3 (Bulk net95 s0 sb0 x6 x7) VLSI_Project_2_to_1_Mux_schematic
    I2 (Bulk net101 s0 sb0 x4 x5) VLSI_Project_2_to_1_Mux_schematic
    I1 (Bulk net67 s0 sb0 x2 x3) VLSI_Project_2_to_1_Mux_schematic
    I0 (Bulk net66 s0 sb0 x0 x1) VLSI_Project_2_to_1_Mux_schematic
ends VLSI_Project_16_to_1_Mux_schematic
// End of subcircuit definition.

// Library name: VLSI_Project
// Cell name: Param_Inverter
// View name: schematic
subckt Param_Inverter VDD VSS in out
parameters nw=90n nl=50n pw=180n pl=50n
    M5 (out in VSS VSS) NMOS_VTL w=nw l=nl as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
    M4 (out in VDD VDD) PMOS_VTL w=pw l=pl as=1.89e-14 ad=1.89e-14 \
        ps=390.0n pd=390.0n ld=105n ls=105n m=1
ends Param_Inverter
// End of subcircuit definition.

// Library name: VLSI_Project
// Cell name: TB_16_to_1_Mux_BusDC
// View name: schematic
I0 (0 MuxOut 0 0 0 0 net067 net067 net067 net067 net099 net097 net073 \
        net079 net077 net075 net081 net083 net095 net089 net091 net093 \
        net087 net085 net069 net071) VLSI_Project_16_to_1_Mux_schematic
C0 (InvOut 0) capacitor c=pOutCap
VSelect (net067 0) vsource dc=pVDD type=dc
V8 (net069 0) vsource dc=pVSRAM8 type=dc
V9 (net071 0) vsource dc=pVSRAM9 type=dc
V10 (net073 0) vsource dc=pVSRAM10 type=dc
V13 (net075 0) vsource dc=pVSRAM13 type=dc
V12 (net077 0) vsource dc=pVSRAM12 type=dc
V11 (net079 0) vsource dc=pVSRAM11 type=dc
V14 (net081 0) vsource dc=pVSRAM14 type=dc
V15 (net083 0) vsource dc=pVSRAM15 type=dc
V7 (net085 0) vsource dc=pVSRAM7 type=dc
V6 (net087 0) vsource dc=pVSRAM6 type=dc
V3 (net089 0) vsource dc=pVSRAM3 type=dc
V4 (net091 0) vsource dc=pVSRAM4 type=dc
V5 (net093 0) vsource dc=pVSRAM5 type=dc
V2 (net095 0) vsource dc=pVSRAM2 type=dc
V1 (net097 0) vsource dc=pVSRAM1 type=dc
V0 (net099 0) vsource dc=pVSRAM0 type=dc
V26 (net074 0) vsource dc=pVDD type=dc
I77 (net074 0 MuxOut InvOut) Param_Inverter nw=90n nl=50n pw=180n pl=50n
